{"398421":{"#nid":"398421","#data":{"type":"news","title":"Ahmet Ceyhan to Receive Best Paper Award","body":[{"value":"\u003Cp\u003EAhmet Ceyhan has been named the recipient of the 2014 S.C. Sun Best Student Paper Award. A recent graduate of the Georgia Tech School of Electrical and Computer Engineering (ECE), he will be presented with this honor at the 2015 International Interconnect Technology Conference, to be held May 18-21 in Grenoble, France.\u003C\/p\u003E\u003Cp\u003EThe title of Ceyhan\u2019s paper is \u201cImpact of Size Effects in Local Interconnects for Future Technology Nodes: A Study Based on Full-Chip Layouts.\u0022 His coauthors on the paper are his former Ph.D. advisor and ECE Associate Professor Azad Naeemi, ECE Professor Sung Kyu Lim, and Shreepad Panth and\u0026nbsp;Moongon Jung, both ECE Ph.D. students of Dr. Lim\u2019s. Ceyhan graduated with his Ph.D. last December and now works at Intel in Hillsboro, Oregon.\u003C\/p\u003E\u003Cp\u003EHistorically, the resistance-capacitance (RC) delay of electronic chips was dominated by the front-end-of-the-line (FEOL) parameters, such as the resistance of the driver transistor and the receiver load capacitance. With miniaturization of the device and interconnect dimensions for over four decades, the backend-of-the-line (BEOL)\u0026nbsp;RC\u0026nbsp;delay became a critical factor in determining the performances of modern electronic chips.\u003C\/p\u003E\u003Cp\u003EThe resistivity of copper wires increases rapidly at small dimensions due to increasing electron scattering at the grain boundaries and surfaces. This adverse impact of scaling on the resistance, hence delay of wires, prevents fully exploiting the improvement in the intrinsic device performance.\u003C\/p\u003E\u003Cp\u003EIn this paper, the team built multiple predictive standard cell and interconnect libraries down to the 7-nm technology node to enable early investigation of the electronic chip performance using commercial electronic design automation tools. Using these libraries, they built layouts for multiple benchmark circuits to study the sensitivity of the circuit performance and power dissipation to multiple interconnect technology parameters at ultra-scaled technology nodes.\u003C\/p\u003E","summary":null,"format":"limited_html"}],"field_subtitle":"","field_summary":[{"value":"\u003Cp\u003ERecent ECE Ph.D. graduate Ahmet Ceyhan has been named the recipient of the 2014 S.C. Sun Best Student Paper Award.\u003C\/p\u003E","format":"limited_html"}],"field_summary_sentence":[{"value":"Recent ECE Ph.D. graduate Ahmet Ceyhan has been named the recipient of the 2014 S.C. Sun Best Student Paper Award."}],"uid":"27241","created_gmt":"2015-04-22 09:58:25","changed_gmt":"2016-10-08 03:18:03","author":"Jackie Nemeth","boilerplate_text":"","field_publication":"","field_article_url":"","dateline":{"date":"2015-04-22T00:00:00-04:00","iso_date":"2015-04-22T00:00:00-04:00","tz":"America\/New_York"},"extras":[],"hg_media":{"398391":{"id":"398391","type":"image","title":"Ahmet Ceyhan","body":null,"created":"1449246371","gmt_created":"2015-12-04 16:26:11","changed":"1475895115","gmt_changed":"2016-10-08 02:51:55","alt":"Ahmet Ceyhan","file":{"fid":"75733","name":"ceyhan_photo.jpg","image_path":"\/sites\/default\/files\/images\/ceyhan_photo.jpg","image_full_path":"http:\/\/tlwarc.hg.gatech.edu\/\/sites\/default\/files\/images\/ceyhan_photo.jpg","mime":"image\/jpeg","size":4748734,"path_740":"http:\/\/tlwarc.hg.gatech.edu\/sites\/default\/files\/styles\/740xx_scale\/public\/images\/ceyhan_photo.jpg?itok=M4-DFaZB"}}},"media_ids":["398391"],"related_links":[{"url":"http:\/\/www.iitc-conference.org\/","title":"2015 International Interconnect Technology Conference"},{"url":"http:\/\/www.gatech.edu\/","title":"Georgia Tech"},{"url":"http:\/\/www.ece.gatech.edu\/","title":"School of Electrical and Computer Engineering"}],"groups":[{"id":"1255","name":"School of Electrical and Computer Engineering"}],"categories":[{"id":"130","name":"Alumni"},{"id":"134","name":"Student and Faculty"},{"id":"8862","name":"Student Research"},{"id":"145","name":"Engineering"},{"id":"149","name":"Nanotechnology and Nanoscience"},{"id":"135","name":"Research"},{"id":"150","name":"Physics and Physical Sciences"}],"keywords":[{"id":"124561","name":"2015 International Interconnect Technology Conference"},{"id":"124551","name":"Ahmet Ceyhan"},{"id":"5518","name":"Azad Naeemi"},{"id":"109","name":"Georgia Tech"},{"id":"166855","name":"School of Electrical and Computer Engineering"},{"id":"171018","name":"Sung Kyu Lim"}],"core_research_areas":[{"id":"39451","name":"Electronics and Nanotechnology"}],"news_room_topics":[],"event_categories":[],"invited_audience":[],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[{"value":"\u003Cp\u003EJackie Nemeth\u003C\/p\u003E\u003Cp\u003ESchool of Electrical and Computer Engineering\u003C\/p\u003E\u003Cp\u003E404-894-2906\u003C\/p\u003E\u003Cp\u003E\u003Ca href=\u0022mailto:jackie.nemeth@ece.gatech.edu\u0022\u003Ejackie.nemeth@ece.gatech.edu\u003C\/a\u003E\u003C\/p\u003E","format":"limited_html"}],"email":["jackie.nemeth@ece.gatech.edu"],"slides":[],"orientation":[],"userdata":""}}}