The title of Ceyhan’s paper is “Impact of Size Effects in Local Interconnects for Future Technology Nodes: A Study Based on Full-Chip Layouts." His coauthors on the paper are his former Ph.D. advisor and ECE Associate Professor Azad Naeemi, ECE Professor Sung Kyu Lim, and Shreepad Panth and Moongon Jung, both ECE Ph.D. students of Dr. Lim’s. Ceyhan graduated with his Ph.D. last December and now works at Intel in Hillsboro, Oregon.

Historically, the resistance-capacitance (RC) delay of electronic chips was dominated by the front-end-of-the-line (FEOL) parameters, such as the resistance of the driver transistor and the receiver load capacitance. With miniaturization of the device and interconnect dimensions for over four decades, the backend-of-the-line (BEOL) RC delay became a critical factor in determining the performances of modern electronic chips.

The resistivity of copper wires increases rapidly at small dimensions due to increasing electron scattering at the grain boundaries and surfaces. This adverse impact of scaling on the resistance, hence delay of wires, prevents fully exploiting the improvement in the intrinsic device performance.

In this paper, the team built multiple predictive standard cell and interconnect libraries down to the 7-nm technology node to enable early investigation of the electronic chip performance using commercial electronic design automation tools. Using these libraries, they built layouts for multiple benchmark circuits to study the sensitivity of the circuit performance and power dissipation to multiple interconnect technology parameters at ultra-scaled technology nodes.