{"43312":{"#nid":"43312","#data":{"type":"event","title":"Timing Closure in Chip Design","body":[{"value":"\u003Cp\u003E\u003Cstrong\u003ETITLE:\u003C\/strong\u003E  Timing Closure in Chip Design\n\u003C\/p\u003E\n\u003Cp\u003E\u003Cstrong\u003ESPEAKER:\u003C\/strong\u003E  Dr. Stephan Held (University of Bonn)\n\u003C\/p\u003E\n\u003Cp\u003E\u003Cstrong\u003EABSTRACT:\u003C\/strong\u003E\n\u003C\/p\u003E\n\u003Cp\u003EA central characteristic of a computer chip is the speed at which it processes data, determined by the time it takes electrical signals to travel through the chip. A major challenge in the design of a chip is to achieve timing closure, that is to find a physical realization fulfilling the speed specifications.\n\u003C\/p\u003E\n\u003Cp\u003EWe give an overview over the major tasks for optimizing the performance of computer chips and present several new algorithms. For the topology generation of repeater trees, we introduce a variant of the Steiner tree problem and present fast algorithm that balances efficiently between the resource consumption and performance.\n\u003C\/p\u003E\n\u003Cp\u003EAnother indispensable task is gate sizing, a discrete optimization problem with nonlinear or PDE constraints, for which a fast heuristic is introduced. The effectiveness in practice is demonstrated by comparing with newly developed lower bounds for the achievable delay.\n\u003C\/p\u003E\n\u003Cp\u003EWe conclude with a variant of the time-cost tradeoff problem from project management. In contrast to the usual formulation cycles are allowed. We present a new method to compute the time-cost tradeoff curve in such instances using combinatorial algorithms. Several problems in chip design can be modeled as time-cost tradeoff problems, e.g. threshold voltage optimization of plane assignment. \u003C\/p\u003E","summary":null,"format":"limited_html"}],"field_subtitle":"","field_summary":[{"value":"Timing Closure in Chip Design","format":"limited_html"}],"field_summary_sentence":[{"value":"Timing Closure in Chip Design"}],"uid":"27187","created_gmt":"2009-10-12 20:37:46","changed_gmt":"2016-10-08 01:47:34","author":"Anita Race","boilerplate_text":"","field_publication":"","field_article_url":"","field_event_time":{"event_time_start":"2008-10-21T16:00:00-04:00","event_time_end":"2008-10-21T17:00:00-04:00","event_time_end_last":"2008-10-21T17:00:00-04:00","gmt_time_start":"2008-10-21 20:00:00","gmt_time_end":"2008-10-21 21:00:00","gmt_time_end_last":"2008-10-21 21:00:00","rrule":null,"timezone":"America\/New_York"},"extras":[],"groups":[{"id":"1242","name":"School of Industrial and Systems Engineering (ISYE)"}],"categories":[],"keywords":[{"id":"5660","name":"algorithms"},{"id":"3251","name":"chip"}],"core_research_areas":[],"news_room_topics":[],"event_categories":[{"id":"1795","name":"Seminar\/Lecture\/Colloquium"}],"invited_audience":[],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[{"value":"\u003Cstrong\u003EAnita  Race\u003C\/strong\u003E\u003Cbr \/\u003EH. Milton Stewart School of Industrial and Systems Engineering\u003Cbr \/\u003E\u003Ca href=\u0022http:\/\/www.gatech.edu\/contact\/index.html?id=ar9\u0022\u003EContact Anita  Race\u003C\/a\u003E","format":"limited_html"}],"email":[],"slides":[],"orientation":[],"userdata":""}}}