{"52543":{"#nid":"52543","#data":{"type":"event","title":"HPC Seminar: Kunal Agrawal","body":[{"value":"\u003Cp\u003E\n\u003C\/p\u003E\n\u003Cp\u003E\u003Cbr \/\u003EPRESENTER: \u00a0\u00a0\u003Ca href=\u0022http:\/\/people.csail.mit.edu\/kunal\/\u0022\u003EKunal Agrawal\u003C\/a\u003E\u003Cbr \/\u003E\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Massachusetts Institute of Technology \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u003Cbr \/\u003E\u003C\/p\u003E\n\u003Cp\u003E\u0022Scheduling and Synchronization for Multicore Processors\u0022\u003Cbr \/\u003E\u003Cbr \/\u003EABSTRACT: \u00a0Traditionally, due to its complexity, parallel programming has been an exclusive domain of expert programmers. However, many hardware vendors are shifting towards building multicore computers, which creates an enormous pressure to create platforms that enable ordinary programmers to write scalable, portable and efficient parallel programs easily. \u00a0Developing correct and efficient parallel programs is difficult since the programmers often have to manage low-level details like scheduling and synchronization explicitly. \u00a0\u003Cbr \/\u003E\u00a0\u003Cbr \/\u003ERecent advances in parallel programming abstractions, like dynamic multithreading, \u00a0stream programming and transactional memory allow the programmers to \u00a0specify their programs in a high-level manner without worrying about \u00a0the low-level scheduling and synchronization details. These new abstractions place a heavier burden on the system, since the system is responsible for efficient and correct scheduling and synchronization of programs. \u00a0\u003Cbr \/\u003E\u00a0\u003Cbr \/\u003EThis talk will present work on provably good schedulers and transactional memory system designs.\u003C\/p\u003E\n\u003Cp\u003EBIO: \u00a0Kunal Agrawal is a final year PhD student at MIT Computer Science and Artificial Intelligence Laboratory. She works with Prof. Charles Leiserson in the Supercomputing Technologies Group. \u00a0She is interested in both theoretical and practical aspects of parallel computing and has worked on various topics such as scheduling, resource allocation, transactional memory, cache-aware and cache-oblivious streaming. \u00a0Her other interests include parallel algorithms and data structures, cache-oblivious algorithms, and contention management.\u003C\/p\u003E\n\u003Cp\u003E\u00a0\u003C\/p\u003E\n\u003Cp\u003EEddie Vail\u003Cbr \/\u003EAdministrative Coordinator\u003Cbr \/\u003EGeorgia Institute of Technology\u003Cbr \/\u003ESchool of Computer Science\u003Cbr \/\u003E266 Ferst Drive\u003Cbr \/\u003EKACB, Room 3404\u003Cbr \/\u003EAtlanta, Georgia 30332\u003Cbr \/\u003EOffice: \u00a0404-894-6711\u003Cbr \/\u003EFax: \u00a0404-385-6506\u003Cbr \/\u003EEmail: \u00a0\u003Ca href=\u0022evail@cc.gatech.edu\u0022\u003Eevail@cc.gatech.edu\u003C\/a\u003E\u003C\/p\u003E","summary":null,"format":"limited_html"}],"field_subtitle":"","field_summary":"","field_summary_sentence":"","uid":"27154","created_gmt":"2010-02-11 15:51:51","changed_gmt":"2016-10-08 01:49:49","author":"Louise Russo","boilerplate_text":"","field_publication":"","field_article_url":"","field_event_time":{"event_time_start":"2009-03-12T12:00:00-04:00","event_time_end":"2009-03-12T13:00:00-04:00","event_time_end_last":"2009-03-12T13:00:00-04:00","gmt_time_start":"2009-03-12 16:00:00","gmt_time_end":"2009-03-12 17:00:00","gmt_time_end_last":"2009-03-12 17:00:00","rrule":null,"timezone":"America\/New_York"},"extras":[],"groups":[{"id":"47223","name":"College of Computing"}],"categories":[],"keywords":[],"core_research_areas":[],"news_room_topics":[],"event_categories":[],"invited_audience":[],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[{"value":"Eddie Vail","format":"limited_html"}],"email":[],"slides":[],"orientation":[],"userdata":""}}}