{"560061":{"#nid":"560061","#data":{"type":"event","title":"P.h.D. Dissertation Defense - Syed Minhaj Hassan","body":[{"value":"\u003Cp\u003E\u003Cstrong\u003ETitle:\u0026nbsp;\u003C\/strong\u003E \u003Cem\u003EExploiting On-Chip Memory Concurrency in 3D Manycore Architectures\u003C\/em\u003E\u003C\/p\u003E\u003Cp\u003E\u003Cstrong\u003ECommittee: \u003C\/strong\u003E\u003C\/p\u003E\u003Cp\u003EDr. Sudhakar Yalamanchili, ECE, Chair, Advisor\u003Cstrong\u003E\u003Cbr \/\u003E\u003C\/strong\u003E\u003C\/p\u003E\u003Cp\u003EDr. Saibal Mukhopadhyay, ECE\u003C\/p\u003E\u003Cp\u003EDr. Tushar Krishna, ECE\u003C\/p\u003E\u003Cp\u003EDr. Hyesoon Kim, ECE\u003C\/p\u003E\u003Cp\u003EDr. Santosh Pande, CoC\u003C\/p\u003E\u003Cp\u003EDr. Richard Vuduc\u003Cstrong\u003E, \u003C\/strong\u003ECoC\u003Cstrong\u003E\u003Cbr \/\u003E\u003C\/strong\u003E\u003C\/p\u003E\u003Cp\u003E\u003Cstrong\u003EAbstract:\u003Cbr \/\u003E\u003C\/strong\u003E\u003C\/p\u003E\u003Cp\u003EThe objective of this thesis is to optimize the uncore of 3D many-core architectures. More specifically, we note that technology trends point to large increases in memory-level concurrency. This in turn affects the design of the multi-core interconnect and organization of the memory hierarchy. The work addresses the need for re-optimization in the presence of this increase in concurrency of the memory system.\u0026nbsp;\u003Cbr \/\u003E \u003Cbr \/\u003E First, we observe that 2D network latency and inefficient parallelism management in the current 3D designs are the main bottlenecks to fully exploit the potentials of 3D. To that end, we\u0026nbsp;propose\u0026nbsp;an extremely low-latency, low-power, high-radix router and present its various versions for different network typologies and configurations. We also explore optimizations and techniques to reduce the traffic in the network. Second, we\u0026nbsp;propose\u0026nbsp;a reorganization of the memory hierarchy and use simple address space translations to regulate locality, bandwidth and energy trade-offs in highly concurrent 3D memory systems. Third, we analyze the rise in temperature of 3D memories and propose variable-rate per-bank refresh management that exploits variability in temperature to reduce 3D DRAM\u0027s refresh power and extend its operating range to higher temperatures.\u003C\/p\u003E\u003Cp\u003E\u003Cstrong\u003E\u003Cbr \/\u003E\u003C\/strong\u003E\u003C\/p\u003E","summary":null,"format":"limited_html"}],"field_subtitle":"","field_summary":"","field_summary_sentence":[{"value":"Exploiting On-Chip Memory Concurrency in 3D Manycore Architectures"}],"uid":"30865","created_gmt":"2016-08-08 10:30:30","changed_gmt":"2016-10-08 02:18:40","author":"Jacqueline Trappier","boilerplate_text":"","field_publication":"","field_article_url":"","field_event_time":{"event_time_start":"2016-08-22T14:00:00-04:00","event_time_end":"2016-08-22T14:00:00-04:00","event_time_end_last":"2016-08-22T14:00:00-04:00","gmt_time_start":"2016-08-22 18:00:00","gmt_time_end":"2016-08-22 18:00:00","gmt_time_end_last":"2016-08-22 18:00:00","rrule":null,"timezone":"America\/New_York"},"extras":[],"groups":[{"id":"434381","name":"ECE Ph.D. Dissertation Defenses"}],"categories":[],"keywords":[{"id":"121411","name":"gradute students"},{"id":"100811","name":"Phd Defense"}],"core_research_areas":[],"news_room_topics":[],"event_categories":[{"id":"1788","name":"Other\/Miscellaneous"}],"invited_audience":[{"id":"78771","name":"Public"}],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[],"email":[],"slides":[],"orientation":[],"userdata":""}}}