{"664751":{"#nid":"664751","#data":{"type":"event","title":"Ph.D. Proposal Oral Exam - Piyush Kumar","body":[{"value":"\u003Cp\u003E\u003Cstrong\u003ETitle:\u0026nbsp; \u003C\/strong\u003E\u003Cem\u003EModeling and benchmarking of spintronic devices for memory and in-memory compute applications\u003C\/em\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003ECommittee:\u0026nbsp; \u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Naeemi, Advisor\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Davis, Chair\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Khan\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003EAbstract: \u003C\/strong\u003EThe objective of the proposed research is to model and benchmark spintronic devices from materials and devices to circuits and application-level. We present a comprehensive model for spin current generation and transport in spin-orbit torque (SOT) devices while considering various nanoscale effects such as incomplete current redistribution, interface scattering, and local variation in material properties. We also provide a thickness optimization metric for SOT layer, quantifying it in terms of its resistivity and spin diffusion length. At the device-level, we evaluate various trade-offs among write current, time, and error rate for SOT-MRAM based on experimentally validated micromagnetic simulations. Moreover, we discuss about area saving schemes for SOT-MRAM based on voltage-controlled magnetic anisotropy (VCMA) effect and spin-transfer torque (STT). We study the read performance of SOT-MRAM array and quantify it in terms of oxide thickness. We benchmark the area and write performance of SOT-MRAM based memory arrays against other competing memories such as STT-MRAM, magneto-electric (ME) MRAM, and SRAM. Finally, at the application-level, we propose novel ternary content addressable memory (TCAM) based on SOT and magneto-electric (ME) effect and benchmark their area and search\/write performance against TCAMs based on other technologies such as STT, SRAM, and FeFET.\u003C\/p\u003E\r\n","summary":null,"format":"limited_html"}],"field_subtitle":"","field_summary":"","field_summary_sentence":[{"value":"Modeling and benchmarking of spintronic devices for memory and in-memory compute applications"}],"uid":"28475","created_gmt":"2023-01-13 21:50:47","changed_gmt":"2023-01-13 21:50:47","author":"Daniela Staiculescu","boilerplate_text":"","field_publication":"","field_article_url":"","field_event_time":{"event_time_start":"2023-01-24T14:00:00-05:00","event_time_end":"2023-01-24T16:00:00-05:00","event_time_end_last":"2023-01-24T16:00:00-05:00","gmt_time_start":"2023-01-24 19:00:00","gmt_time_end":"2023-01-24 21:00:00","gmt_time_end_last":"2023-01-24 21:00:00","rrule":null,"timezone":"America\/New_York"},"extras":[],"groups":[{"id":"434371","name":"ECE Ph.D. Proposal Oral Exams"}],"categories":[],"keywords":[{"id":"102851","name":"Phd proposal"},{"id":"1808","name":"graduate students"}],"core_research_areas":[],"news_room_topics":[],"event_categories":[{"id":"1788","name":"Other\/Miscellaneous"}],"invited_audience":[{"id":"78771","name":"Public"}],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[],"email":[],"slides":[],"orientation":[],"userdata":""}}}