Committee: 

Dr. Naeemi, Advisor      

Dr. Davis, Chair

Dr. Khan

Abstract: The objective of the proposed research is to model and benchmark spintronic devices from materials and devices to circuits and application-level. We present a comprehensive model for spin current generation and transport in spin-orbit torque (SOT) devices while considering various nanoscale effects such as incomplete current redistribution, interface scattering, and local variation in material properties. We also provide a thickness optimization metric for SOT layer, quantifying it in terms of its resistivity and spin diffusion length. At the device-level, we evaluate various trade-offs among write current, time, and error rate for SOT-MRAM based on experimentally validated micromagnetic simulations. Moreover, we discuss about area saving schemes for SOT-MRAM based on voltage-controlled magnetic anisotropy (VCMA) effect and spin-transfer torque (STT). We study the read performance of SOT-MRAM array and quantify it in terms of oxide thickness. We benchmark the area and write performance of SOT-MRAM based memory arrays against other competing memories such as STT-MRAM, magneto-electric (ME) MRAM, and SRAM. Finally, at the application-level, we propose novel ternary content addressable memory (TCAM) based on SOT and magneto-electric (ME) effect and benchmark their area and search/write performance against TCAMs based on other technologies such as STT, SRAM, and FeFET.