667330 event 1681415279 1682696939 <![CDATA[Ph.D. Proposal Oral Exam - Raveesh Garg]]> Title:  Architecture and Mapping Support for Exploiting Inter-Operation Data Reuse in AI, HPC and Graph Applications on Spatial Accelerators

Committee: 

Dr. Krishna, Advisor     

Dr. Kim, Chair

Dr. Vuduc

Dr. Pellauer

]]> The objective of the proposed research is to formalize and propose architectures and mapping strategies that exploit data reuse opportunities beyond a single matrix multiplication for AI, HPC and Graph applications on Spatial Accelerators. Sparse and Dense matrix multiplications are prime operations for a variety of applications spanning Graph Analytics, High-Performance Computing and Artificial Intelligence. Hardware accelerators and Mappers for Deep Learning have gained traction because of the huge reuse opportunities offered in matrix multiplication operations inside Deep Learning operations which provide considerable reduction in data movement compared to CPU and GPU since their architecture can inherently exploit data reuse inside a single layer/operation. However, several HPC and Graph applications have matrix multiplications that are highly skewed and certain matrices that are square and highly sparse which dramatically hampers the arithmetic intensities of the individual matrix multiplication operations. Thus, these applications incur high data movement if executed operation-by-operation even the reuse inside an individual operation is maximized. Moreover, even for Deep Learning applications on the edge, operation-by-operation execution can hamper the performance and energy, since these platforms have limited on-chip memory as a result of which DRAM accesses increase. Therefore, the objective of this thesis is to explore reuse opportunities between the operations in AI, HPC and graph applications.

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