667494 event 1682358940 1682447153 <![CDATA[Ph.D. Dissertation Defense - Daehuyn Kim]]> Title:  Processing in memory architecture for neural networks and on-chip learning acceleration

Committee:

Dr. Saibal Mukhopadhyay, ECE, Chair, Advisor

Dr. Shimeng Yu, ECE

Dr. Tushar Krishna, ECE

Dr. Visvesh Sathe, ECE

Dr. Satish Kumar, ME

]]> These days, numerous devices like smart cameras, smart speakers, and wearable devices leverage machine learning. However, the neural networks employed for machine learning can be computationally expensive and require tremendous memory capacity. Furthermore, these devices require personalized neural networks for greater accuracy, but due to power, performance, area and memory constraints, it's challenging for edge devices to train these networks independently. Currently, most devices connect to a server for neural network training, leading to issues with security, data privacy, reliability, and compatibility. As edge devices become more prevalent, addressing these challenges is critical for ensuring the continued growth and success of machine learning applications in various fields. The objective of this research is to show that processing-in-memory (PIM) architecture with on-chip learning has high performance and is computationally efficient in accelerating machine learning applications. PIM architecture can effectively address the limitations faced by these resource-limited devices by allowing computation to occur within the memory itself, rather than relying on traditional Von Neumann architectures. This results in reduced data movement and lower energy consumption, while also improving overall performance. Furthermore, on-chip learning enables local training of machine learning models on the device itself, mitigating the issues related to security, data privacy, reliability, and compatibility that stem from server-side training. By combining PIM architecture and on-chip learning, this research aims to demonstrate a viable solution for enabling efficient and secure machine learning on resource-constrained devices. This thesis aims to explore the potential of PIM architecture with on-chip learning to address the growing demand for efficient hardware solutions for neural networks. By developing and demonstrating their capabilities through prototype chips, this work contributes to the advancement of neural network hardware design and provides valuable insights for future research in this area.

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