12:00 PM EST
via
Teams
Meeting ID: 288 847 186 38
Passcode: tATXiZ
will be held the
MASTER’S THESIS DEFENSE
for
Ramón Alfonso Sosa
“A MAP TO RELIABLE CHIP-TO-PACKAGE CU-PILLAR INTERCONNECTIONS WITH SINTERED NANOPOROUS-CU CAPS”
Committee Members:
Dr. Vanessa Smet, ME (Co-Advisor)
Dr. Antonia Antoniou, ME (Co-Advisor)
Dr. Rao Tummala, ECE (Co-Advisor)
Dr. Preet Singh, MSE
Abstract: With a continuous drive towards increased performance and miniaturization pushing the frontiers of system-level integration, emerging high-performance computing systems will require chip-to-substrate interconnection solutions that can reliably operate at higher operating temperatures (>100℃), current densities (>106 A/cm2), and at finer pitches (<20 µm) expected in these architectures, well beyond the fundamental limits of traditional solder-based interconnections. All-Cu interconnections, the natural next off-chip interconnection node, have been successfully implemented at the foundry level via the now mature hybrid bonding process, though its reliance on expensive chemical-mechanical planarization (CMP) processes and material incompatibilities preclude it from being used at the package level, where the levels of non-coplanarity and warpage that exist cannot be addressed in this manner. Thus, there exists a need for an all-Cu interconnection technology with enhanced tolerance to non-coplanarities that can be used at the chip-to-substrate level.
Sintered Nanoporous-Cu interconnections are proposed in this research to address this grand challenge. Nanoporous-Cu (NP-Cu) is a spongelike material with an elastic modulus an order of magnitude lower than that of bulk-Cu, giving it enhanced compliance during assembly and allowing it to readily deform under modest pressures to accommodate package-level non-coplanarities. Additionally, the nanoscale structure of NP-Cu allows it to sinter at low temperatures, and is not reliant on organic stabilizers, unlike nanoscale particle systems, minimizing the risk of voiding due to volatiles.
This thesis presents two parallel thrusts in demonstrating the applicability of nanoporous-Cu as a suitable bonding interface material for chip-to-substrate all-Cu interconnections. The first is a demonstration of the manufacturability of nanoporous-Cu, which can be fabricated through an in-house designed electrodeposition process at fine-pitch of a Cu-Zn precursor alloy and subsequent chemical dealloying of this precursor. An extensive characterization of the wafer-scale Cu-Zn bumping process is presented, including the global, local, and within bump variations in composition of the electrodeposited Cu-Zn precursor, and a study that characterizes the incidence of nodule-type defects on these Cu-Zn bumps.
The second thrust is an exploration of the bonding parameter space for the formation of robust sintered NP-Cu interconnections. Through this study, the conventional thermocompression bonding process, which relies on extensive time under pressure, commonly used for direct Cu-Cu bonding is replaced by a hot-placement and pressureless sintering approach, which yields low-resistance, high-strength sintered NP-Cu interconnections at modest temperatures and lower placement pressures compared to bulk-Cu bonding. Finally, an evaluation of the reliability of these sintered NP-Cu interconnections under thermal aging, electromigration testing, and thermal cycling testing is presented.
In summary, this work provides a pathway for reliable, fine-pitch all-Cu interconnections at the package level with enhanced tolerance to non-coplanarities using sintered nanoporous-Cu as a bonding interface material.
]]>