{"671329":{"#nid":"671329","#data":{"type":"event","title":"Ph.D. Proposal Oral Exam - Tzu Han Wang","body":[{"value":"\u003Cp\u003E\u003Cspan\u003E\u003Cspan\u003E\u003Cspan\u003E\u003Cstrong\u003E\u003Cspan\u003ETitle:\u0026nbsp; \u003C\/span\u003E\u003C\/strong\u003E\u003Cem\u003E\u003Cspan\u003EHigh-resolution wide-band hybrid analog-digital converter with reduced peripheral circuit complexity\u003C\/span\u003E\u003C\/em\u003E\u003C\/span\u003E\u003C\/span\u003E\u003C\/span\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cspan\u003E\u003Cspan\u003E\u003Cstrong\u003E\u003Cspan\u003ECommittee:\u0026nbsp; \u003C\/span\u003E\u003C\/strong\u003E\u003C\/span\u003E\u003C\/span\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cspan\u003E\u003Cspan\u003E\u003Cspan\u003EDr. \u003C\/span\u003E\u003Cspan\u003EShaolan Li\u003C\/span\u003E\u003Cspan\u003E, Advisor\u003C\/span\u003E\u0026nbsp; \u003C\/span\u003E\u003C\/span\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cspan\u003E\u003Cspan\u003E\u003Cspan\u003EDr. \u003C\/span\u003E\u003Cspan\u003ESathe\u003C\/span\u003E\u003Cspan\u003E, Chair\u003C\/span\u003E\u003C\/span\u003E\u003C\/span\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cspan\u003E\u003Cspan\u003E\u003Cspan\u003EDr. \u003C\/span\u003E\u003Cspan\u003EMukhopadhyay\u003C\/span\u003E\u003C\/span\u003E\u003C\/span\u003E\u003C\/p\u003E\r\n","summary":"","format":"limited_html"}],"field_subtitle":"","field_summary":[{"value":"\u003Cp\u003E\u003Cspan\u003E\u003Cspan\u003EThe proposed research\u0027s objective is to first reduce the complexity and power overhead of the recent noise-shaping SAR (NS-SAR) analog-to-digital converter (ADC) design. Another major objective is to surpass the limitation of the relatively low speed of the NS-SAR ADCs owing to their extra steps of residue processing. Therefore, a novel ADC architecture with the NS-SAR mechanism is proposed in this proposal. First, the pipeline ADC architecture merging with a two-channel time-interleaving beck-end NS-SAR ADC is employed. Such arrangements address the speed obstacles of the NS-SAR and inherently mitigate the complexity of the loop filter design. Second, using a sub-ranging capacitive digital-to-analog converter as the digital result holder, the proposed pipeline scheme\u0027s interstage gain is reused as a driver for the back-end sampling. This technique has the potential to largely mitigate the sampling kT\/C noise of the front-end stage ADC, which is beneficial to the ADC power, noise, and resolution concern.\u003C\/span\u003E\u003C\/span\u003E\u003C\/p\u003E\r\n","format":"limited_html"}],"field_summary_sentence":[{"value":"High-resolution wide-band hybrid analog-digital converter with reduced peripheral circuit complexity"}],"uid":"28475","created_gmt":"2023-11-30 19:26:24","changed_gmt":"2023-11-30 19:26:39","author":"Daniela Staiculescu","boilerplate_text":"","field_publication":"","field_article_url":"","field_event_time":{"event_time_start":"2023-12-08T10:00:00-05:00","event_time_end":"2023-12-08T12:00:00-05:00","event_time_end_last":"2023-12-08T12:00:00-05:00","gmt_time_start":"2023-12-08 15:00:00","gmt_time_end":"2023-12-08 17:00:00","gmt_time_end_last":"2023-12-08 17:00:00","rrule":null,"timezone":"America\/New_York"},"location":"Online","extras":[],"related_links":[{"url":"https:\/\/teams.microsoft.com\/l\/meetup-join\/19%3ameeting_N2U0MDM1NGUtZWIyMC00NTcyLWE4MWItZWQxYWQ1ZWZlZGQz%40thread.v2\/0?context=%7b%22Tid%22%3a%22482198bb-ae7b-4b25-8b7a-6d7f32faa083%22%2c%22Oid%22%3a%2205ca73bb-3544-484d-aef2-6d2dbd1f0b31%22%7d","title":"Microsoft Teams Meeting link"}],"groups":[{"id":"434371","name":"ECE Ph.D. Proposal Oral Exams"}],"categories":[],"keywords":[{"id":"102851","name":"Phd proposal"},{"id":"1808","name":"graduate students"}],"core_research_areas":[],"news_room_topics":[],"event_categories":[{"id":"1788","name":"Other\/Miscellaneous"}],"invited_audience":[{"id":"78771","name":"Public"}],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[],"email":[],"slides":[],"orientation":[],"userdata":""}}}