671329 event 1701372384 1701372399 <![CDATA[Ph.D. Proposal Oral Exam - Tzu Han Wang]]> Title:  High-resolution wide-band hybrid analog-digital converter with reduced peripheral circuit complexity

Committee: 

Dr. Shaolan Li, Advisor 

Dr. Sathe, Chair

Dr. Mukhopadhyay

]]> The proposed research's objective is to first reduce the complexity and power overhead of the recent noise-shaping SAR (NS-SAR) analog-to-digital converter (ADC) design. Another major objective is to surpass the limitation of the relatively low speed of the NS-SAR ADCs owing to their extra steps of residue processing. Therefore, a novel ADC architecture with the NS-SAR mechanism is proposed in this proposal. First, the pipeline ADC architecture merging with a two-channel time-interleaving beck-end NS-SAR ADC is employed. Such arrangements address the speed obstacles of the NS-SAR and inherently mitigate the complexity of the loop filter design. Second, using a sub-ranging capacitive digital-to-analog converter as the digital result holder, the proposed pipeline scheme's interstage gain is reused as a driver for the back-end sampling. This technique has the potential to largely mitigate the sampling kT/C noise of the front-end stage ADC, which is beneficial to the ADC power, noise, and resolution concern.

]]> <![CDATA[]]> https://teams.microsoft.com/l/meetup-join/19%3ameeting_N2U0MDM1NGUtZWIyMC00NTcyLWE4MWItZWQxYWQ1ZWZlZGQz%40thread.v2/0?context=%7b%22Tid%22%3a%22482198bb-ae7b-4b25-8b7a-6d7f32faa083%22%2c%22Oid%22%3a%2205ca73bb-3544-484d-aef2-6d2dbd1f0b31%22%7d 434371 1788 102851 1808